Instructions involved in a general purpose register (GPR) such as integer registers are widely used in instruction set architectures (ISA) such as x86 architecture. Most x86 GPR (e.g., integer registers other than x87 or single instruction multiple data (SIMD)/advanced vector extension (AVX) registers) operations write to an integer register as well as manipulate an x86 arithmetic flag register. For example, an addition instruction such as ADD instruction modifies a flag (e.g., OF, SF, ZF, AF, CF, and PF flags) and updates a GPR destination. An increment instruction such as INC also modifies a flag (e.g., OF, SF, ZF, AF, and PF) and updates a GPR destination. Often, this flag modification is unnecessary and yet adds complexity and potential performance implications due to unnecessary dependency chains.
An instruction can also be conditionally executed by a processor based on one or more conditions. Typically, x86 GPR instructions require multiple opcodes or instructions in order to perform a conditional execution, for example, based on one or more test fields as shown in a condition code table in FIG. 6. Such a requirement may consume more resources and reduce the performance of a processor.